A liquid crystal panel includes a TFT (Thin Film Transistor) array substrate and a color film substrate therein, and there are liquid crystals dripped between the color film substrate and the TFT array substrate. In order to enable the liquid crystal panel to display, a driving voltage is required to be input to the TFT array substrate by a driving circuit, in which a gate turn-on voltage is needed to be input onto a gate scan line on the TFT array substrate and a data voltage is needed to be input onto a data scan line thereon.
As an example, the present invention uses a signal OE2 as a second-order gate turn-on voltage control signal to explain the current implementation. The driving circuit of the liquid crystal panel includes mainly a timing controller, a power supply unit, a gate driving IC (Integrated Circuit) and a source driving IC. The timing chart of the driving voltage output by the driving circuit is as shown in FIG. 1, in which it is carried on from the left to the right in time order. Wherein, a rising edge of STV is a signal for the start of each frame, the signal OE2 controls a second-order gate turn-on voltage (VON), CPV is a gate shift signal. When a rising edge of STV comes so as to start scanning of one frame, a rising edge of CPV comes so as to control the start of scanning of one row each time when one falling edge of the signal OE2 comes. There is one horizontal blanking period between the horizontal display time of the current row and the horizontal display time of the next row, and the horizontal display time for each row plus the horizontal blanking period is one horizontal cycle. After completion of the scanning of the current row, the next rising edge of the signal OE2 comes when the current row just enters the horizontal blanking period, and the gate voltage is reduced. Further, the next rising edge of CPV comes, when the next falling edge of the signal OE2 comes, so as to control the start of scanning of the next row. In FIG. 1, Gn and Gn+1 indicate the changes of levels of gate scan lines of the n-th row and the (n+1)-th row, respectively, in which Th is a vertical cycle.
As shown in FIG. 1, there is a vertical planking period, i.e. a blanking time, between two successive frames, that is, a vertical display time (Thd) subtracted from a vertical cycle (Th). Within the vertical blanking period, the voltages of gate scan lines of each row keep at −8V (a pinch-off voltage VOFF). In the present invention, the description is made taking the original pinch-off voltage of a TFT of −8V as an example, and the scanning of the next frame is not started until STV reaches a rising edge again.
In the course of driving a liquid crystal panel using the above driving manner, it is found that there is at least the following problem in existing techniques.
In the course that the data voltage input on a data scan line is input to a pixel electrode through a TFT, if the data voltage has certain regularity, for example, data voltages input continuously for a relatively long time are all at high levels, polarities of ions passing through a TFT channel will be fixed. When there are matters such as impurities in the TFT channel, they will attract or exclude these ions, resulting in that accumulation of ions occurs in the TFT channel (i.e. an active layer of the TFT). Accordingly, the accumulated ions will form an electric field around, leading to the interference to the electric field between the pixel electrode and a common electrode on the color film substrate and influencing finally on the display effect of the liquid crystal panel.